Tuesday, 23 June 2015

BARC & IIT Bombay RA Experience
Went to Bombay a day before. Stayed in IIT Bombay because I had few facebook friends. To my luck , even they had BARC Interview. We all went there.  There was initially a check up of all the certificates and to and from tickets for travel allowance.  The interview went on like this 

1. Graph of Voltage across capacitor vrs time with different values of R,L,C in series RLC Circuit.
2. Super Diode
3. A lot of confusing questions on whether some Mosfet is depletion or enhancement type.
4. Set up and Hold up time
5. Signals and Systems questions were mostly on finding the Fourier series and transform based on symmetry.
6. Some quality Control System questions.

With this.. My tour of India completed. 

Starting from Bangalore to Madras to Delhi to Bombay.....................



Before putting some thing else, I want to summarize as to what all offers I had in my hand

1. IIT Bombay - Communications ( 1st round) and Electronics Systems ( 4th round)
2. IIT Madras - Communications ( 1st round)
3. IIT Delhi - IEC, VDTT
4. IIT Kharagpur - Micro Electronics
5. IISC Bangalore - Communications and Networking

The below given experience is by my friend K. Bharadwaj. I needn't had to go to IIT Bombay RA. He have put his thoughts. He tasted the success in IIT Bombay RA and I have put his experience.

M.Tech (EE)IIT BOMBAY (RA) Experience
                                                                                                                                       
It is usually very difficult getting VLSI in old IIT's for ranks above 200(my rank is 295 and score 803 in EC).For such people,IITB provides a golden oppurtunity with M.Tech  as RA(Research Assistant).It's a 3 year course but is nowhere different to two year M.tech as TA(Teaching Assistant).Curriculum,Coursework and placements are all same except that RA has to spend one more year.As an RA,one has to take less courses per semester(3 as against 5 for TA) but has to spend 20 hours of work  per week as against 8 hours of work for TA.There are two kinds of Research assistants
1.Institue RA
-One has to work in labs like electronics lab,VLSI lab to help undergraduate students in performing experiments.These are concerned with day to day activities of lab including maintainence.Even System administrator comes under this RA.
2.Project RA
-Professors have funded projects from various sources.As a project RA,one has to assist these professors in project and in administrative work also as told by respective guide.

Now,the difference between them is in chosing guide.Project RA will be assigned a guide at selection and cannot be changed.He is expected to do his thesis work in same area as project alloted while Institute RA has the freedom of choosing guide.

Selection Process :
Cutoff is put in gate score and are called.This year(2015),cutoff  is 660(GEN),596(OBC),440(SC/ST).It means ranks upto 1200 can also be called in GEN
There will be a written test and Interview as part of selection process.

Written Test:It has objective type questions in which some may require answers in one or two sentences.Time duration is 2 hours
Consisted of 3 sections
Section 1 consists of MATHS,APTITUDE,CONTROL SYSTEMS,ELECTRICAL MACHINES (50 marks as far as  i remember)
Section 2 consists of LINUX Basics(commands,networking ),Communication,DSP questions(50 marks ..or may be 60.. i dont remember exactly)
Section 3 consists of Analog ,digital and electronic devices (50 marks)

There is no need to attempt all sections.Because it is not expected for a core electrical guy to know communications and vice versa.It is essential to score in the area for which you gave preference.Questions level were easy-medium but time was the constraint.this year,paper was lengthy enough that scoring 50 in whole paper is great.I guess my score would be around 45

Now shortlisting happens on following criteria
Institute RA- 50 % gate score ,50 % written test
Project RA-75 % gate score,25 % written test
Till last year 2:1 people were called for the interviews for the number of positons available.But this time it was 3:1.This year number of positions for institute RA are 36(5 were for only electrical)
and 21 for Project RA(5 were pure electrical projects).120 odd people were shortlisted for Institute RA whereas 63 for project RA(around 300 people gave written test).Your name can appear in both lists but will be interviewed only once in which you have to indicate preferences.

This is atleast 2 day process in which first day will be written test.Resullts will be in website by Night.Next day,we assembled at hall and we were given forms for giving preferences in Institute RA(Electronics lab,VLSI lab,System administrator,Communication lab).Projects(abstracts were given to us) seperately for institute RA and Project RA.we were  then addressed by HOD who surprised us with a new proposal this year to check laboratory skills for people who preferred electronics lab in 1st or 2nd choices.We were taken to WEL lab and were given an experiment to perform.It was implementing 3 bit counter using a 4 bit counter  (not the usual kind but its easy.just that idea has to strike)and connecting it to a DAC circuit given in question and verifying with theoritical values.

INTERVIEW :There were 16 panels and we are alloted based on our preferences in the form filled earlier.Each panel had 2 members.If you are shortlisted for both institute as well as project(and dual degree (mtech +phd )also had interviews in same timings.You have to write same test as RA if u have applied and have been invited for that also),the panel asks you preference .I preferred project RA as i had interest in a proj 'chip design for Physiological monitoring(healthcare)' and had previous experience with my mini project in same area.I was asked to introduce myself and  I told about my education and projects I did as major and mini.They were interested and asked me about the circuit i used for mini project which had biasing,filtering and amplication.I was asked about the opamp used in my project and why was it specifically used(it was noiseless).We basically had a discussion rather than being interviewed.Then the professor asked me a basic RC filter question and asked me to draw outputs on R and C for a square wave input.Then asked when it would function as Integrator and differentiator and what happens if the case is opposite(RC>>T,RC<<T).All this took around 30 mins .Only one prof asked me all this.I got to know that other prof is asking about digital questions if we mentioned digital as interest.They asked me what I was doing for the last one year as i was already passout last year.Thats all.They said they were done.So simple it seems na ;).It was the simplest interview of all the ones i had.They were asking only basic questions.So if you have good gate score and performed reasonable well in written test and interview you can get seat easily.If you have less  gate score,dont worry but perform well in written test and interview.Results will be annouced in a week or two.

I am here by putting up few links that may be useful for students

http://asic.co.in/Index_files/Digital_interview_questions1.htm ( Some very good questions with explanations for Digital electronics. Will also help you clarify your concepts )
http://asic-soc.blogspot.in/ ( Digital questions )
Go and have a blast @ GATE.

Finally, hope this journey was good.....

Any query please feel free to ask and subscribe to this blog for more information.


             
IIT Delhi - Part 5 -  Interview Experiences


The results came out after 3 days.

Yes.  I tasted bitter in terms of loss of Texas and Cadence. But these were not un happy scenes for me because I knew how the things went inside in the interview.

But to my happiness finally, I got selected for VDTT - with the external sponsorship from Cypress Semi Conductors. Also, I got IEC.

Thank God..... So finally I got selected for something through rounds of interview..

Thanks..




The next post would be about the only Govt Job that I attended - BARC.
 It is located in Bombay. It is one of the finest things. Although it is very good program but from the ECE point of view, all it would leave you is with a satisfaction that you are having Govt Job and nothing much.


Lets go to Bombay and taste some wada pav............................
                                           
IIT Delhi - Part 4 - Interview Experiences
I know many of you would be waiting as to what happened and how things went..

I was called for Cypress Semicondutors Interview

Cypress Interview Experience: 

 He asked me about hold time, set up time constraints and how they come into picture and what will you do to mitigate with it. Actually these questions would have been new to most of the Btech guys and even they were new to me also, had I not gone to IISC Bangalore. 

They never asked these, but I got it here. So that's the reason, I would always ask people to attend interviews. Because you never know what happens when and what is coming your way.
It was followed up with some normal questions on comparators. I was asked to design a comparator using MOSFET.

Then few normal questions on CMOS Inverter. I was going well.

Then other questions about BJT. Few questions on Body Effect, different regions of operation of MOSFET and BJT.

Also the last question was "Why Mtech , leaving job in a company"

I some how felt very confident about the interview. I immediately called up my father and told that I would be in easily.


Cadence Interview

They had 2 panels - One for software and other for Analog profile. I some how, unable to recongize the labels of the panels, went to software profile. They asked C, Linked Lists, Data Structures.
I kept mum for a while and answered few things. But I never felt I was in.

They offered me a bottle of Yummy Apple Juice. I couldn't resist taking it, after all atleast Apple Juice should be for me, if not a position in Cadence.

Texas Interview:

I was shocked first of all as to how and why Texas called me because I kept them as 4 th preference. There was only 1 question that he was asking me since the starting. I and the person were discussing only about the same circuit. I could not solve to the extent to which he needed. It was again about transient analysis in Network Theory.

Then there were few questions on CMOS Inverter and the Body Effect. But they were too much beyond my capability.

Qualcomm didn't call me.


IIT Delhi - Part 3 - Interview Experiences
So the day started with the continuation of the previous day.

VDTT is a sponsored program, where in the first round of Interviews will be conducted by the IIT Delhi Professors and the second round of interviews will be done the by Sponsors and the Internal MHRD Project Profs.

VDTT 2nd round:

So although, it was supposed to start @ 9 am in the morning, it started after lunch. So in the mean while, I went to IEC interview (skipping my lunch). To my luck, there were the few professors who interviewed me in VDTT first round. They recognized me and asked me whether I was through in the 1st round of VDTT. I replied kindly that the first round I got in and the next rounds are going on.

The Professors were impressed with my rank and also few questions normally about MOSFET were asked and I was told at that point of time only that you are offered IEC and if you don't fare well in VDTT next round, take it or else leave it fastly.

With the first success, I walked into VDTT interview room.

There were too many presentations.
 Companies :    Qualcomm, Texas, Cypress, Cadence.
 Projects: Nanoscale Devices, Smart Cane/Refreshable Braille Display,Mass Spectrometer                                                 


So out of the 300 odd students that came into the initial phase, roughly 25 students were in for the next round and roughly 10 seats are available..

Lets fight...          

We were asked to keep the preferences to the 7 Sponsors. I have kept Cypress in the top and followed with Cadence, Qualcomm, Texas.

Frankly I was afraid with Texas because of the previous experience in IIT Madras. At the same time, I was dis appointed that I was un prepared to attend the Interview of Qualcomm because I was not in touch with Communications for a while.

                In the next post, I will share my Interview. How things went. ..
                                                     How was the story of my failure agian... and a success story from it..
IIT Delhi - Part 2 - Interview Experiences

So I came to the room after the VDTT Interview and slept in the room without disturbing others who were having different interviews

I woke up @ 5 and along with 2 others went to the VDTT Office for the results @ 6pm on the same day. The results got delayed and it went on to 9pm finally. We waited out of curiosity and then you know what happened...

                  I AM IN ......




So after a lot of failures, I had some hope now. 
I had two VLSI Interviews on hand the next day and Computer Technology Interview also.

I filled myself with all the inspiration. I thought to myself, yes this is moment may be for which I am waiting. I need to give my best.

I need to thank one of my friend's friend Kalyan Kota. He was helpful in making a lot of decisions.


So the day ended for many but it never ended for me because I was anxious, afraid, hopeful for a brighter tomorrow.

I read upto late night. - I always had only 2 books for my Electronics - Sedra & Smith and Razavi.

So the next day. 
             
                                   Let me check it out.. 

 Hope things go fine. - IEC / VDTT.
                                                              Please.. 







IIT Delhi - Par1 - Interview Experiences
Before going to Delhi, just 2 days back I got Kharagpur VLSI, so I was a bit uncertain whether I will be going because I was comfortable with VLSI in top 5 IITs. But then to my luck, the reservation was confirmed and I along with 2 others have gone there. From Hyderabad, it almost took 30 hours journey.


I had a lot of Interviews in IIT Delhi – IEC, VDTT, JTM, Computer Technology.

We got into the college 1 day before the Interview. IIT Delhi is good in one aspect that it doesn’t have written tests. I have not been qualifying the tests so far may be because they were written test  ( Jokes are excuses some times)


I have a friend Roopesh Sharma there ( JTM Student and AIR 245 in Gate 2014) . The hostels in IIT Delhi are not that great in terms of look. Food is ok. My friend had luckily made me familiar with few seniors of IEC and VDTT.

I had conversation with few persons of both IEC, VDTT. I came to know about the process but then I had to appear for the process.

VDTT Interview : 
                            Initially they verified our documents and divided us into few groups and each group for each Interview panel. Mine was Panel 2. Initially every panel students were coming out but in our panel there was no one who even went inside. I was the first person as per sequence in my panel.

After a while, I was asked to come into. The Panel had 2 Professors, old enough to make me afraid. I greeted them and even they followed it up with a nice little smile, that made me feel a bit relaxed.
I was asked the following questions.


                                    1. Draw CMOS Inverter
                                    2. In the same diagram, now ground and power supply are exchanged?
                                     3. Implement Y = AB+C+D (whole bar) in NMOS,PMOS,CMOS logics
                                       4. If I add 2 sin signals with one of them having frequency f1 and other 2*f1                                               or say some 1000*f1. Then draw the resultant as a diagram.
                                            5. Why CMOS. Why not NMOS or PMOS.

The results where supposed to be announced in the evening. 
               I was waiting upto evening.
I was in an unknown status. Going by my heart, I thought I was in. But then Bangalore and Madras kept me thinking and reminding about my luck again and again...



JTM Interview :
                            Didn't attend the Interview because some how I was confident about VDTT and also even if I don't do VDTT well, I had IEC chance the next day. So, thought of preparing for them rather than going for JTM interview. Because any how even I had to go to Communications, I would go to IIT Bombay or Madras.

                        I will tell about the next part of VDTT in the next post.
                             
                   
  IIT Madras - Interview Experiences
Yes. After the failure of IISC Bangalore, I went to IIT Madras. I came here for Texas Sponsored MS.
It is one of the very good programs in IITs in the field of VLSI. IIT Madras is best for some one interested in Analog Research.  I was prepared for a tough fight. 

I knew mentally that It would be very difficult for me to clear the rounds because the number of people whom they will call is all ECE Rankers < 1000 and all Instrumentation and Electrical guys with Ranks< 750.

There is no reservation for this program. Luckily I haven't had any.

I got there on May 1st itself. I had a friend Charan working in TCS. Both of us roamed around the city and went to sea shore and few other places. It was as if I came there for some other reason. But thanks to him, atleast roamed a lot in Chennai. Thanks for him for a lovely care.

Next day on May 2nd , I went to the College – IIT Madras. In the presentation by the Texas team, they have really made us get goose bumps for the company it is. It produces diverse products and today Texas is in the top position in Analog research and IIT Madras is like heaven for analog research. 

It has 3 gods of Analog – Nagendra Krishnapura, Anirudhan, Shanti Pavan.  Texas came with an offer of employment of 16L after successful completion of MS, although nothing is assured. They will also give us higher stipend of 20K for the first year and 30K for the next 2 years.  

I went to the written test. I was shocked to see the questions. They were not easy but neither were they out of box. I can assure you u can never come across such questions any where in any question bank.


Most of the guys were in the same mood. Don't know what to comment. They were such questions which required us to be theoretically Mr. Perfect, nothing less.

I will update all the questions once I sit back to write all those in a notebook. In the mean while you can refer to the given link. Actually One thing is that Texas will only ask transient analysis and Analog Electronics to a very deep level.


But this was a bit too tougher on my part. I knew that syllabus is Network theory and Analog Electronics. But I could not clear the written round due to my lack of understanding things in even perfect way.

It required a lot of mastery of the subject much better than mine.


But learnt again that I still need to improve.

               With low levels of Confidence and may be in a spot of bother whether I will not be able to manage to get VLSI seat through Interview, I read more for the next time... 

                            Chalo Delhi. next